Caravel Management SoC - Litex

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Overview

This repository contains an implementation of the management area for Caravel. The management area is SoC generated using Litex containing a VexRiscv core with memory, a flash controller and serial peripherals.

Caravel Management Area Block Diagram

Features

  • VexRiscv core with debug port

  • 2 kB SRAM plus 1 kB of DFFRAM

  • XIP SPI Flash controller

  • UART, SPI and GPIO ports

  • 128 port logic analyzer

  • Counter / timer

  • 32-bit Wishbone bus extending to the user project area

  • 6 user interrupts

Processor

The processor core is based on a VexRiscv minimal+debug configuration. The core has been configured with 64 bytes of instruction cache. The core has not been configured with compress or multiply instructions.

Flash Controller

Description

The flash controller supports single mode SPI to a compatible W25Q128JV Flash device. The configuration supports execute-in-place and the CPU reset vector is configured for the beginning of the Flash memory region.

Interrupts (IRQ)

Description

The processor is configured with interrupts for the Uart and Timer devices. It also supports 6 user IRQS extended to the user project.

The corresponding register must be set to enable interrupts from the respective device. The following registers are applicable:

  • reg_timer0_irq_en

  • reg_timer0_irq_en

  • reg_timer0_irq_en

Controller


This device has an EventManager-based interrupt system. Individual modules generate events which are wired into a central interrupt controller.

When an interrupt occurs, you should look the interrupt number up in the CPU- specific interrupt table and then call the relevant module.

Assigned Interrupts

The following interrupts are assigned on this system:

Interrupt

Module

0

TIMER0

1

UART

2

USER_IRQ_0

3

USER_IRQ_1

4

USER_IRQ_2

5

USER_IRQ_3

6

USER_IRQ_4

7

USER_IRQ_5

UART

Description

The UART provide general serial communication with the management SoC. The baud rate is configured at 9600.

The reg_uart_enable must be set in order to run (disabled by default).

reg_uart_enable can be used to read and write data to the port.


Register Listing for UART

Register

Address

UART_RXTX

0xf0005800

UART_TXFULL

0xf0005804

UART_RXEMPTY

0xf0005808

UART_EV_STATUS

0xf000580c

UART_EV_PENDING

0xf0005810

UART_EV_ENABLE

0xf0005814

UART_TXEMPTY

0xf0005818

UART_RXFULL

0xf000581c

UART_RXTX

Address: 0xf0005800 + 0x0 = 0xf0005800

UART_TXFULL

Address: 0xf0005800 + 0x4 = 0xf0005804

TX FIFO Full.

UART_RXEMPTY

Address: 0xf0005800 + 0x8 = 0xf0005808

RX FIFO Empty.

UART_EV_STATUS

Address: 0xf0005800 + 0xc = 0xf000580c

This register contains the current raw level of the rx event trigger. Writes to this register have no effect.

Field

Name

Description

[0]

TX

Level of the tx event

[1]

RX

Level of the rx event

UART_EV_PENDING

Address: 0xf0005800 + 0x10 = 0xf0005810

When a rx event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register.

Field

Name

Description

[0]

TX

1 if a tx event occurred. This Event is triggered on a falling edge.

[1]

RX

1 if a rx event occurred. This Event is triggered on a falling edge.

UART_EV_ENABLE

Address: 0xf0005800 + 0x14 = 0xf0005814

This register enables the corresponding rx events. Write a 0 to this register to disable individual events.

Field

Name

Description

[0]

TX

Write a 1 to enable the tx Event

[1]

RX

Write a 1 to enable the rx Event

UART_TXEMPTY

Address: 0xf0005800 + 0x18 = 0xf0005818

TX FIFO Empty.

UART_RXFULL

Address: 0xf0005800 + 0x1c = 0xf000581c

RX FIFO Full.

SPI Controller

Description

The SPI controller is operated through the reg_spimaster_control and ``reg_spimaster_status’’ registers.

reg_spimaster_rdata and reg_spimaster_wdata are used to read abd write data through to the port.


Register Listing for SPI_MASTER

Register

Address

SPI_MASTER_CONTROL

0xf0004800

SPI_MASTER_STATUS

0xf0004804

SPI_MASTER_MOSI

0xf0004808

SPI_MASTER_MISO

0xf000480c

SPI_MASTER_CS

0xf0004810

SPI_MASTER_LOOPBACK

0xf0004814

SPI_MASTER_CLK_DIVIDER

0xf0004818

SPI_MASTER_CONTROL

Address: 0xf0004800 + 0x0 = 0xf0004800

SPI Control.

Field

Name

Description

[0]

START

SPI Xfer Start (Write 1 to start Xfer).

[15:8]

LENGTH

SPI Xfer Length (in bits).

SPI_MASTER_STATUS

Address: 0xf0004800 + 0x4 = 0xf0004804

SPI Status.

Field

Name

Description

[0]

DONE

SPI Xfer Done (when read as 1).

SPI_MASTER_MOSI

Address: 0xf0004800 + 0x8 = 0xf0004808

SPI MOSI data (MSB-first serialization).

SPI_MASTER_MISO

Address: 0xf0004800 + 0xc = 0xf000480c

SPI MISO data (MSB-first de-serialization).

SPI_MASTER_CS

Address: 0xf0004800 + 0x10 = 0xf0004810

SPI CS Chip-Select and Mode.

Field

Name

Description

[0]

SEL

Value

Description

0b0..001

Chip 0 selected for SPI Xfer.

0b1..000

Chip N selected for SPI Xfer.

[16]

MODE

Value

Description

0b0

Normal operation (CS handled by Core).

0b1

Manual operation (CS handled by User, direct recopy of sel), useful for Bulk transfers.

SPI_MASTER_LOOPBACK

Address: 0xf0004800 + 0x14 = 0xf0004814

SPI Loopback Mode.

Field

Name

Description

[0]

MODE

Value

Description

0b0

Normal operation.

0b1

Loopback operation (MOSI to MISO).

SPI_MASTER_CLK_DIVIDER

Address: 0xf0004800 + 0x18 = 0xf0004818

SPI Clk Divider.

GPIO


Register Listing for GPIO

Register

Address

GPIO_MODE1

0xf0002800

GPIO_MODE0

0xf0002804

GPIO_IEN

0xf0002808

GPIO_OE

0xf000280c

GPIO_IN

0xf0002810

GPIO_OUT

0xf0002814

GPIO_MODE1

Address: 0xf0002800 + 0x0 = 0xf0002800

GPIO Tristate(s) Control.

GPIO_MODE0

Address: 0xf0002800 + 0x4 = 0xf0002804

GPIO Tristate(s) Control.

GPIO_IEN

Address: 0xf0002800 + 0x8 = 0xf0002808

GPIO Tristate(s) Control.

GPIO_OE

Address: 0xf0002800 + 0xc = 0xf000280c

GPIO Tristate(s) Control.

GPIO_IN

Address: 0xf0002800 + 0x10 = 0xf0002810

GPIO Input(s) Status.

GPIO_OUT

Address: 0xf0002800 + 0x14 = 0xf0002814

GPIO Ouptut(s) Control.

Description

A single GPIO port is provided from the Management SoC as general indicator and diagnostic for programming or as a means to control functionality off chip.

One example user case is to set an enable for an off-chip LDO enabling a controlled power-up sequence for the user project.

Debug

Description

Debug support is enabled in the core and can be accessed through a dedicated UART port configured as a wishbone master. The baud rate for the port is 9600.

See the following reference for more information <https://github.com/SpinalHDL/VexRiscv#debugplugin>.

Counter / Timer

Description


Provides a generic Timer core.

The Timer is implemented as a countdown timer that can be used in various modes:

  • Polling : Returns current countdown value to software

  • One-Shot: Loads itself and stops when value reaches 0

  • Periodic: (Re-)Loads itself when value reaches 0

en register allows the user to enable/disable the Timer. When the Timer is enabled, it is automatically loaded with the value of load register.

When the Timer reaches 0, it is automatically reloaded with value of reload register.

The user can latch the current countdown value by writing to update_value register, it will update value register with current countdown value.

To use the Timer in One-Shot mode, the user needs to:

  • Disable the timer

  • Set the load register to the expected duration

  • (Re-)Enable the Timer

To use the Timer in Periodic mode, the user needs to:

  • Disable the Timer

  • Set the load register to 0

  • Set the reload register to the expected period

  • Enable the Timer

For both modes, the CPU can be advertised by an IRQ that the duration/period has elapsed. (The CPU can also do software polling with update_value and value to know the elapsed duration)

Register Listing for TIMER0

Register

Address

TIMER0_LOAD

0xf0005000

TIMER0_RELOAD

0xf0005004

TIMER0_EN

0xf0005008

TIMER0_UPDATE_VALUE

0xf000500c

TIMER0_VALUE

0xf0005010

TIMER0_EV_STATUS

0xf0005014

TIMER0_EV_PENDING

0xf0005018

TIMER0_EV_ENABLE

0xf000501c

TIMER0_LOAD

Address: 0xf0005000 + 0x0 = 0xf0005000

Load value when Timer is (re-)enabled. In One-Shot mode, the value written to this register specifies the Timer’s duration in clock cycles.

TIMER0_RELOAD

Address: 0xf0005000 + 0x4 = 0xf0005004

Reload value when Timer reaches 0. In Periodic mode, the value written to this register specify the Timer’s period in clock cycles.

TIMER0_EN

Address: 0xf0005000 + 0x8 = 0xf0005008

Enable flag of the Timer. Set this flag to 1 to enable/start the Timer. Set to 0 to disable the Timer.

TIMER0_UPDATE_VALUE

Address: 0xf0005000 + 0xc = 0xf000500c

Update trigger for the current countdown value. A write to this register latches the current countdown value to value register.

TIMER0_VALUE

Address: 0xf0005000 + 0x10 = 0xf0005010

Latched countdown value. This value is updated by writing to update_value.

TIMER0_EV_STATUS

Address: 0xf0005000 + 0x14 = 0xf0005014

This register contains the current raw level of the zero event trigger. Writes to this register have no effect.

Field

Name

Description

[0]

ZERO

Level of the zero event

TIMER0_EV_PENDING

Address: 0xf0005000 + 0x18 = 0xf0005018

When a zero event occurs, the corresponding bit will be set in this register. To clear the Event, set the corresponding bit in this register.

Field

Name

Description

[0]

ZERO

1 if a zero event occurred. This Event is triggered on a falling edge.

TIMER0_EV_ENABLE

Address: 0xf0005000 + 0x1c = 0xf000501c

This register enables the corresponding zero events. Write a 0 to this register to disable individual events.

Field

Name

Description

[0]

ZERO

Write a 1 to enable the zero Event

Logic Analyzer

Description

The logic analyzer function provides a flexible means to monitor signals from the user project wrapper or drive them from the management core.

The logic analyzer supports 128 signals mapped to separated GPIO in, out and oeb ports.

==

Register Listing for LA

Register

Address

LA_IEN3

0xf0003000

LA_IEN2

0xf0003004

LA_IEN1

0xf0003008

LA_IEN0

0xf000300c

LA_OE3

0xf0003010

LA_OE2

0xf0003014

LA_OE1

0xf0003018

LA_OE0

0xf000301c

LA_IN3

0xf0003020

LA_IN2

0xf0003024

LA_IN1

0xf0003028

LA_IN0

0xf000302c

LA_OUT3

0xf0003030

LA_OUT2

0xf0003034

LA_OUT1

0xf0003038

LA_OUT0

0xf000303c

LA_IEN3

Address: 0xf0003000 + 0x0 = 0xf0003000

Bits 96-127 of LA_IEN. LA Input Enable

LA_IEN2

Address: 0xf0003000 + 0x4 = 0xf0003004

Bits 64-95 of LA_IEN.

LA_IEN1

Address: 0xf0003000 + 0x8 = 0xf0003008

Bits 32-63 of LA_IEN.

LA_IEN0

Address: 0xf0003000 + 0xc = 0xf000300c

Bits 0-31 of LA_IEN.

LA_OE3

Address: 0xf0003000 + 0x10 = 0xf0003010

Bits 96-127 of LA_OE. LA Output Enable

LA_OE2

Address: 0xf0003000 + 0x14 = 0xf0003014

Bits 64-95 of LA_OE.

LA_OE1

Address: 0xf0003000 + 0x18 = 0xf0003018

Bits 32-63 of LA_OE.

LA_OE0

Address: 0xf0003000 + 0x1c = 0xf000301c

Bits 0-31 of LA_OE.

LA_IN3

Address: 0xf0003000 + 0x20 = 0xf0003020

Bits 96-127 of LA_IN. LA Input(s) Status.

LA_IN2

Address: 0xf0003000 + 0x24 = 0xf0003024

Bits 64-95 of LA_IN.

LA_IN1

Address: 0xf0003000 + 0x28 = 0xf0003028

Bits 32-63 of LA_IN.

LA_IN0

Address: 0xf0003000 + 0x2c = 0xf000302c

Bits 0-31 of LA_IN.

LA_OUT3

Address: 0xf0003000 + 0x30 = 0xf0003030

Bits 96-127 of LA_OUT. LA Ouptut(s) Control.

LA_OUT2

Address: 0xf0003000 + 0x34 = 0xf0003034

Bits 64-95 of LA_OUT.

LA_OUT1

Address: 0xf0003000 + 0x38 = 0xf0003038

Bits 32-63 of LA_OUT.

LA_OUT0

Address: 0xf0003000 + 0x3c = 0xf000303c

Bits 0-31 of LA_OUT.

Memory Regions

Region

Address

Size

dff

0x00000000

0x00000400

sram

0x01000000

0x00000800

flash

0x10000000

0x01000000

hk

0x26000000

0x00100000

user project

0x30000000

0x10000000

csr

0xf0000000

0x00010000

vexriscv_debug

0xf00f0000

0x00000100