CTRL

Register Listing for CTRL

Register

Address

CTRL_RESET

0xf0000000

CTRL_SCRATCH

0xf0000004

CTRL_BUS_ERRORS

0xf0000008

CTRL_RESET

Address: 0xf0000000 + 0x0 = 0xf0000000

Field

Name

Description

[0]

SOC_RST

Write 1 to this register to reset the full SoC (Pulse Reset)

[1]

CPU_RST

Write 1 to this register to reset the CPU(s) of the SoC (Hold Reset)

CTRL_SCRATCH

Address: 0xf0000000 + 0x4 = 0xf0000004

Use this register as a scratch space to verify that software read/write accesses to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578 can be used to verify endianness.

CTRL_BUS_ERRORS

Address: 0xf0000000 + 0x8 = 0xf0000008

Total number of Wishbone bus errors (timeouts) since start.