FLASH_CORE
Register Listing for FLASH_CORE
Register |
Address |
---|---|
FLASH_CORE_MMAP_DUMMY_BITS |
0xf0001800 |
FLASH_CORE_MASTER_CS |
0xf0001804 |
FLASH_CORE_MASTER_PHYCONFIG |
0xf0001808 |
FLASH_CORE_MASTER_RXTX |
0xf000180c |
FLASH_CORE_MASTER_STATUS |
0xf0001810 |
FLASH_CORE_MASTER_PHYCONFIG
Address: 0xf0001800 + 0x8 = 0xf0001808
SPI PHY settings.
Field |
Name |
Description |
---|---|---|
[7:0] |
LEN |
SPI Xfer length (in bits). |
[11:8] |
WIDTH |
SPI Xfer width (1/2/4/8). |
[23:16] |
MASK |
SPI DQ output enable mask (set bits to |
FLASH_CORE_MASTER_STATUS
Address: 0xf0001800 + 0x10 = 0xf0001810
Field |
Name |
Description |
---|---|---|
[0] |
TX_READY |
TX FIFO is not full. |
[1] |
RX_READY |
RX FIFO is not empty. |